Memory designs based on a negative differential resistance (“NDR”) cell, such as a thyristor cell, have been introduced as a replacement for conventional DRAM and SRAM. A thyristor-based RAM may be effective in either or both SRAM and DRAM applications.
If a thyristor-based memory cell having a data logic 0 (“D0”) state is read immediately after a write of a D0 to such cell, a bit error or bit fail may result. By “immediately after,” it is generally meant a next clock cycle after the clock cycle associated with the write of a D0. While it is possible for bit failure to occur on a subsequent clock cycle to the next clock cycle following such a write clock cycle, likelihood of such bit failure tends to decrease after the clock cycle immediately following such write clock cycle.
It should generally be understood that writing a D0 or writing a data logic 1 (“D1”) state to a thyristor-based memory cell is dependent on voltage of a base, such as a “p-base” of such thyristor-based memory cell. Generally, a D0 means a relatively low voltage on such p-base, and a D1 means a relatively high voltage on such p-base. In a D0 state, a thyristor-based memory cell is supposed to stay in an OFF state, namely conduct little to no current from anode node to cathode node, when read. In a D1 state, a thyristor-based memory cell is supposed to stay in an ON state, namely conduct a substantial amount of current from anode node to cathode node, when read. Accordingly, when a D0 is written to a thyristor-based memory, p-base voltage is at a lowest voltage state. If one or more nearest neighbor thyristor-based memory cells in an array thereof are at D1, then junctions associated with borders of such nearest neighbor thyristor-based memory cells have the highest potential difference and electric field between the thyristor cells. Accordingly, if such a thyristor-based memory cell at D0 is susceptible to “punch through,” then such an electrostatic influence from the neighboring cell may promote a bit failure. However, it should be understood that in a D0 state, the junctions are reverse biased, irrespective of the state of a neighboring cell. If a neighboring cell is at D1, it may increase the depletion in reverse bias junctions making another cell more likely to fail.
Accordingly, it would be desirable and useful to provide means to avoid or at least mitigate against bit errors or bit failure associated with an erroneous change of state from a D0 state to a D1 state of a thyristor-based memory cell.